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1 ds8110a-00 may 2009 www.richtek.com RT8110A pin configurations (top view) sop-8 (exposed pad) ordering information note : richtek pb-free and green products are : ` rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ` suitable for use in snpb or pb-free soldering processes. 2 3 4 5 8 7 6 gnd 9 phase gnd lgate ugate boot fb vcc vin RT8110A package type sp : sop-8 (exposed pad-option 1) operating temperature range p : pb free with commercial standard g : green (halogen free with commer- cial standard) - wide input range synchronous buck dc/dc pwm controller general description the RT8110A is a fixed-frequency pwm controller with integrated mosfet drivers for single power rail synchronous single-phase buck converter. this part features an internal regulator that allows wide input voltage range operation. the RT8110A utilizes voltage-mode control with internal compensation to simplify the converter design. an internal 0.8v reference voltage allows low output voltage application. the switching frequency is fixed at 600khz to reduce the external passive component size to save board space. the RT8110A provides under voltage protection, current limit, over current protection and over temperature protection. the low-side mosfet r ds(on) is used to sense the inductor current for over current protection. features z z z z z 10v to 23v wide input voltage range z z z z z 0.8v internal reference z z z z z internal soft start z z z z z high dc gain voltage mode pwm control z z z z z fixed 600khz switching frequency z z z z z fast transient response z z z z z fully dynamic 0 to 80% duty cycle z z z z z over current protection z z z z z under voltage protection z z z z z over temperature protection z z z z z rohs compliant and 100% lead (pb)-free applications z set-top box power supplies z pc subsystem power supplies z cable modems, dsl modems z dsp and core communication processor power supplies z memory power supplies z personal computer peripherals z industrial power supplies z low voltage distributed power supplies free datasheet http:///
2 ds8110a-00 may 2009 www.richtek.com RT8110A functional pin description typical application circuit pin no. pin name pin function 1 phase switching node of the buck converter. this pin is also used to monitor the voltage drop across the low-side mosfet for over current protection. 2 ugate gate drive pin for high-side mosfet. 3, 9 (exposed pad) gnd signal and power ground of the ic. all voltage levels are referenced with respect to this pin. the exposed pad must be soldered to a large pcb and connected to gnd for maximum power dissipation. 4 lgate gate drive pin for low-side mosfet. 5 vcc internal regulator output pin, typically 5.5v. vin is regulated to vcc by the internal regulator. vcc is the main bias supply of the ic. this pin also provides power for the low-side mosfet gate driver. connect a ceramic capacitor to this pin. the voltage at this pin is monitored for power on reset (por). 6 fb inverting input of the error amplifier. this pin is connected to the joint of output voltage divider resistors to set the output voltage. the voltage at this pin is also monitored for under voltage protection. 7 vin this pin is internally connected to the collector of integrated bjt, which is designed to withstand 23v to provide a regulated 5.5v voltage to vcc pin. 8 boot this pin provides power to the high-side mosfet gate driver. a bootstrap circuit is used to drive the high-side mosfet. v o u t 2 1 4 6 3 , e x p o s e d p a d ( 9 ) v c c v i n f b u g a t e r t 8 1 1 0 a l g a t e g n d 5 7 8 b o o t p h a s e l v i n c 4 c b o o t q 1 q 2 c o u t + + c i n d c 1 c 3 c 5 c 2 r 2 r 1 r 3 free datasheet http:///
3 ds8110a-00 may 2009 www.richtek.com RT8110A function block diagram soft-start and fault logic gate control logic + - + - vcc r oc i oc 1.5v boot fb phase gnd lgate vin ugate vcc power- on reset por + - 0.5v + - + - + 0.8v ref uvp pwm gm v cc regulator oscillator s1l oc ph_m ss eo vcc 5k free datasheet http:///
4 ds8110a-00 may 2009 www.richtek.com RT8110A electrical characteristics (v in = 5v, t a = 25c, unless otherwise specified) absolute maximum ratings (note 1) z supply voltage, v cc ------------------------------------------------------------------------------------------------------ 7v z supply voltage, v in ------------------------------------------------------------------------------------------------------- 30v z phase ---------------------------------------------------------------------------------------------------------------------- ? 3v to 24v z boot ------------------------------------------------------------------------------------------------------------------------ 30v z input/output voltage ------------------------------------------------------------------------------------------------------ 0.3v to 7v z power dissipation, p d @ t a = 25 c sop-8 (exposed pad) -------------------------------------------------------------------------------------------------- 1.333w z package thermal resistance (note 4) sop-8 (exposed pad), ja ---------------------------------------------------------------------------------------------- 75 c/w sop-8 (exposed pad), jc --------------------------------------------------------------------------------------------- 15 c/w z junction temperature ----------------------------------------------------------------------------------------------------- 150 c z lead temperature (soldering, 10 sec.) ------------------------------------------------------------------------------- 260 c z storage temperature range -------------------------------------------------------------------------------------------- ? 65 c to 150 c z esd susceptibility (note 2) hbm (human body mode) ---------------------------------------------------------------------------------------------- 2kv mm (ma chine mode) ------------------------------------------------------------------------------------------------------ 200v recommended operating conditions (note 3) z supply voltage, v in ------------------------------------------------------------------------------------------------------- 10v to 23v z junction temperature range -------------------------------------------------------------------------------------------- ? 40 c to 125 c z ambient temperature range -------------------------------------------------------------------------------------------- 0 c to 70 c parameter symbol test conditions min typ max units v in supply current po wer su pply c urre nt i cc u gate, lgate open -- 3 6 ma input voltage range v in 10 -- 23 v regulated output voltage v cc -- 5.5 -- v power-on reset vcc threshold voltage r ising -- 4.7 -- v vcc threshold hysteresis -- 0.9 -- v reference reference voltage v ref 0.784 0.8 0.816 v oscillator free running frequency f sw 480 600 720 khz ramp amplitude v osc -- 2.2 -- v error ampl ifi er e/a transconductance gm n ote 5 -- 0.3 -- ms open loop dc gain a o n ote 5 60 90 -- db to be continued free datasheet http:///
5 ds8110a-00 may 2009 www.richtek.com RT8110A note 1. stresses listed as the above ? absolute maximum ratings ? may cause permanent damage to the device. these are for stress ratings. functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. note 2. devices are esd sensitive. handling precaution is recommended. note 3. the device is not guaranteed to function outside its operating conditions. note 4. ja is measured in the natural convection at t a = 25 c on a high effective four layers thermal conductivity test board of jedec 51-7 thermal measurement standard. the case position of jc is on the exposed pad of sop-8 (exposed pad) package. note 5. guarantee by design. parameter symbol test conditions min typ max units mosfet gate driver ugate drive source r ugat esr v boot ? ph ase = 5v v boot ? v ugat e = 1v -- 3 4.5 ugate drive sink r ugat esk v ugate ? phase = 1v v boot ? phase = 5v -- 2 3 lgate drive source r lgatesr v cc ? v lgate = 1v, -- 4 6 lgate drive sink r lgatesk v lgate = 1v -- 2 4 ugate drive source i ugatesr v boot ? v ugate = 5v -- 0.72 -- a ugate drive sink i ugatesk v ugate ? phase = 5v -- 0.82 -- a lgate drive source i lgatesr v vcc ? v lgate = 5v -- 0.65 -- a lgate drive sink i lgatesk v lgate ? gnd = 5v -- 1.18 -- a protection over current threshold v oc sense phase pin voltage ?? ? 250 -- mv maximum duty cycle -- 80 -- % uvp threshold fb falling -- 0.5 0.6 v soft start soft start interval t ss 1 3 6 ms free datasheet http:///
6 ds8110a-00 may 2009 www.richtek.com RT8110A typical operating characteristics v out = 2.5v, i load = 5a power on time (2ms/div) ugate (20v/div) v cc (5v/div) v in (10v/div) v out (2v/div) v in = 23v v out = 2.5v, i load = 5a power on time (2ms/div) ugate (20v/div) v cc (5v/div) v in (5v/div) v out (2v/div) v in = 12v short circuit over current protection v out (200mv/div) time (2ms/div) lgate (5v/div) ugate (20v/div) inductor current (5a/div) single rail, short output then power on over current protection v out (2v/div) time (2ms/div) lgate (5v/div) ugate (20v/div) inductor current (5a/div) low-side mosfet r ds(on) = 32m single power rail v in = 12v, v out = 2.5v under voltage protection lgate (2v/div) ugate (20v/div) vcc (5v/div) time (4ms/div) dual rail, power off converter input v out = 2.5v, i load = 5a power on sequence lgate (5v/div) ugate (20v/div) time (2ms/div) v out = 2.5v, i load = 0.5a v in (10v/div) v out (1v/div) dual rail, controller v in is ready then power on converter input v in (10v/div) v in = v cc = 12v, low-side mosfet r ds(on) = 32m free datasheet http:///
7 ds8110a-00 may 2009 www.richtek.com RT8110A switching frequency vs. temperature 480 500 520 540 560 580 600 620 640 660 680 700 720 -50 -25 0 25 50 75 100 125 temperature switching frequency (khz) reference voltage vs. temperature 0.784 0.788 0.792 0.796 0.800 0.804 0.808 0.812 0.816 -50 -25 0 25 50 75 100 125 temperature reference voltage (v) vcc vs. temperature 5.46 5.48 5.50 5.52 5.54 5.56 5.58 5.60 -50 -25 0 25 50 75 100 125 temperature vcc (v) v out = 2.5v, no load ( c) ( c) v in = 12v v in = 23v v out = 2.5v, no load v in = 12v v in = 23v v out = 2.5v, no load ( c) v in = 12v v in = 23v free datasheet http:///
8 ds8110a-00 may 2009 www.richtek.com RT8110A applications information the RT8110A is a wide input voltage range, voltage-mode pwm controller with integrated mosfet gate drivers for single-phase synchronous buck converter. it features an internal regulator, which provides regulated vcc from a wide input range of vin to power the controller. this part provides internal soft start, internal loop compensation and protection functions. internal vcc regulator RT8110A can operate with input voltage range from 10v to 23v in single input power applications. the input voltage at vin pin is internally connected to the integrated bipolar junction transistor and is then regulated to 5.5v by the internal regulator to support vcc. vcc is used as the power of internal control logic circuit and low-side mosfet gate driver. it is recommended to add a 2.2 f ceramic capacitor to the vcc pin. power-up and soft start the power-on-reset (por) function continuously monitors the voltage at the vcc pin. when vcc rises and exceeds the por threshold, the controller initiates its power-up sequence with continuous low-frequency, small-width pulses at ugate (~6khz). these pulses are used for converter power stage input voltage (v in ) detection. if v in is applied, the voltage at phase pin will rise and fall due to these detection pulses. a digital counter and a comparator are used to record the number of times that voltage at phase pin exceeds the internally-defined voltage level (~1.5v). if the voltage at phase pin exceeds and below the internally-defined voltage level for two times, detection pulse stops and v in is recognized to be ready. once v in is ready, soft-start will then initiate after a time delay. otherwise the detection pulse at ugate continues. RT8110A provides internal soft start function. figure 1 shows the pwm comparator and the operational transconductance amplifier (ota). the ota has three inputs: reference voltage v ref , feedback voltage signal fb, and soft start signal ss. during the soft start interval, the feedback voltage signal tracks the ss signal. because ss signal rises from zero in monotone, therefore the pwm duty cycle will increase gradually at start up to prevent large inrush current. when fb voltage reaches v ref , soft figure 1. transconductance amplifier and pwm comparator. + - + + v ref ss v out r1 r2 fb gm transconductance error amplifier pwm comparator compensation network + - bootstrap circuit figure 2 shows the bootstrap gate drive circuit supplied from vcc. the bootstrap circuit consists of bootstrap capacitor c boot and blocking diode d boot . the selection of these two components can be done after choosing the high-side mosfet. the bootstrap capacitor must have a voltage rating that is able to withstand twice the maximum supply voltage. the capacitance is determined using the following equation : gate boot bootstrap q c = v where q gate is the total gate charge of the high-side mosfet, and v bootstrap is the voltage drop allowed on the high-side mosfet gate drive. for example, the total gate charge for mosfet is about 30nc. for an allowed voltage drop of 300mv, the required bootstrap capacitance is 0.1 f. referring to figure 2, the bootstrap diode must be able to block the power stage supply voltage plus any peak ringing voltage at the phase pin when q1 is turned on. therefore, the voltage rating of the bootstrap diode should be at least 1.5 to twice of the power stage supply voltage. since the r ds(on) of mosfet will be higher if the gate-to- source driving voltage is lower, a bootstrap diode with larger forward voltage results in lower gate drive voltage, higher on-resistance and lower efficiency. therefore, the forward voltage of the bootstrap diode should be low. fast recovery diode or schottky diode which has low forward voltage is recommended for the bootstrap diode. start ends and fb will track v ref . the typical soft start time interval is 3ms free datasheet http:///
9 ds8110a-00 may 2009 www.richtek.com RT8110A figure 2. gate driver and bootstrap circuit phase boot ugate lgate vcc + - vcc regulator pwm comparator c boot v in d boot q1 q2 current limit and over current protection (ocp) RT8110A provides current limit and over current protection. the low-side mosfet on-resistance is used to sense the inductor current. once the high-side mosfet is turned off, the low-side mosfet is turned on when dead time ends. inductor current then flows through the low- side mosfet and build a voltage drop across the drain and source (phase to gnd). this voltage is sensed to monitor the inductor peak current. as shown in figure 3, the over current threshold is determined internally by the current source i oc and the internal resistor r oc . the current source i oc flows through resistor r oc and builds voltage v oc (=i oc x r oc ) which is referenced to the phase pin. when load current increase and the sensed phase voltage falls below v oc in one switching cycle, controller will treat this as an over current event. each over current event will cause one ugate pwm pulse to be prohibited, but has no influence on lgate signal, it still keep switching. ugate pwm pulse is permitted when over current event does not exist. if over current event does not occur in the next switching cycle, ugate will switch again, or the ugate pulse will still be prohibited. in this way, inductor peak current will be limited. if the load current further increases, either over current protection or under voltage protection will be tripped. the over current protection will be tripped when the over current event occurs for continuously four pwm pulses. when ocp is triggered, both ugate and lgate go low, controller will initiate re-start in hiccup way. for ocp, controller has three times of hiccupped re-start before shutdown. controller will latch off after three times of hiccup. the ocp threshold is determined by the r ds(on) of low- side mosfet. the inductor peak current i peak can be calculated using the following equation. figure 3. over current protection mechanism + - v cc i oc r oc +- i oc x r oc phase v in q1 q2 l + - i l x r ds(on) oc comparator under voltage protection (uvp) after soft start completes, the fb voltage is monitored for uvp. the uvp function has a 10 s delay time and the threshold is typically 0.5v. if fb voltage falls below the threshold, uvp will be tripped, both ugate and lgate go low and then the hiccupped re-start will be initialized. the uvp re-start behavior is different from that of ocp; the controller will always initiate re-start in a hiccupped way. over temperature protection (otp) the RT8110A integrates thermal protection function. the over temperature protection is a latched protection and its threshold is typically 160 c. when otp is triggered, controller shuts down, both high-side and the low-side mosfet are turned off. note that i peak is the inductor peak current, therefore, i peak should be set to be greater than i out(max) + ( i)/2 to prevent false tripping, where i is the output inductor ripple current, and i out(max) is the maximum load current. since mosfet r ds(on) increases with temperature, the controller will trip ocp/current limit earlier at high temperature. to avoid false tripping, considering the highest junction temperature of the mosfet and calculate the ocp threshold to select r ds(on) . oc peak ds(on) v i r ? free datasheet http:///
10 ds8110a-00 may 2009 www.richtek.com RT8110A input capacitor selection the input capacitor not only reduces the noise and voltage ripple on the input, but it also reduces the peak current drawn from the power source. the input capacitor must meet the rms current requirement imposed by the switching current defined by the following equation: out out in out rms in iv(vv) i = v ? the input rms current varies with load and input voltage, and has a maximum of half the output current when output voltage is equal to half the input voltage. in addition, ceramic capacitor is recommended for high frequency decoupling because of its low equivalent series resistance and low equivalent inductance. these ceramic capacitors should be placed physically between and close to the drain of high-side mosfet and the source of the low- side mosfet. the voltage rating is another key parameter for the input capacitor. in general, choose the voltage rating with 50% higher than the input voltage for the input capacitor to ensure the operation reliability. output voltage setting the converter output voltage can be set by the external voltage divider resistors. figure 4 shows the connection of the output voltage divider resistors. the controller will regulate the output voltage according to the ratio of the voltage divider resistors r1 and r2. figure 4. voltage divider resistors + - gm + v ref v out r1 r2 fb transconductance error amplifier if r1 is given and the output voltage is specified, then r2 can be determined using the following equation : ref out ref v r2 = r1 vv ?? ?? ? ?? feedback compensation and output capacitor selection the RT8110A is a voltage-mode pwm controller, it uses operational transconductance amplifier (ota) with internal compensation network to eliminate external compensation components. the compensation network is used to shape the gain curve to obtain accurate dc regulation, fast load transient response and maintain stability. figure 5 shows the bode plot of the modulation gain, compensation gain and the close loop gain. a stable control loop has a close gain curve with a -20db/decade slope at the crossover frequency and the phase margin is greater than 45 . figure 5. bode plot of loop gain. 0 f lc f esr f z1 gain (db) freq.(log) modulation gain compensation gain close loop gain f z2 f p2 f p1 f c + - gm + v ref r1 r2 transconductance error amplifier + v in r load esr c out dcr l q1 q2 output capacitor c3 output inductor c p 10pf r s 50k c s 4nf pwm generator & mosfet driver r3 optional figure 6. simplified diagram for synchronous buck converter with internal compensation network figure 6 illustrates the simplified synchronous buck converter using ota with internal compensation. the feedback loop consists of zin (r1, r2 and c1), ota and the internal compensation network z fb (r s , c s , c p ). the value of internal compensation component is : r s 50k, c s 4nf, c p 10pf. free datasheet http:///
11 ds8110a-00 may 2009 www.richtek.com RT8110A referring to figure 5, the location of pole and zero of the lc filter and the compensation network can be determined using the following equations. the inductor and the output capacitor create a double pole at f lc : the equivalent series resistance (esr) of the output capacitor creates a zero at f esr : the internal compensation network introduces a zero at f z1 : the internal compensation network also introduces a pole at f p2 : the external r3 and c3 introduces a zero at f z2 : the external r3 and c3 introduces a pole at f p1 : since the internal compensation values are given, the close loop crossover frequency and phase margin can be obtained after inductance and capacitance are determined. external r3 and c3 are used to adjust the crossover frequency and phase margin. the typical design procedure is described as follows. step 1 : collect system parameters such as switching frequency, input voltage, output voltage, output voltage ripple, and full load current. step 2 : determine the output inductance value. the recommended inductor ripple current is between 10% and 30% of the full load output current. the inductance can be calculated using the following equation. step 3 : determine the output capacitance and the esr. neglecting the equivalent series inductance of the output capacitor, the output capacitance c out can be approximately determined using the following equations. step 4 : calculate the crossover frequency, phase margin and check stability. calculate the frequency of f lc , f esr , f z1 , f z2 , f p1 and f p2 with selected inductance, capacitance and esr. then plot the bode diagram of close loop gain to check crossover frequency and phase margin. in general, the crossover frequency f c is between 1/10 and 1/5 of the switching frequency (60khz to 120khz); and the phase margin should be greater than 45 . if the bandwidth and phase margin are not within an acceptable range, add r3 and c3 to slightly adjust the crossover frequency and phase margin. if the crossover frequency and phase margin still can't meet the requirement after tuning r3 and c3, re-select the esr and c out (mainly) or inductance value to change the location of f lc and f esr then repeat step 4. note that the output voltage ripple and transient response should still meet the specification after changing esr, c out or l. thermal considerations for continuous operation, do not exceed absolute maximum operation junction temperature. the maximum power dissipation depends on the thermal resistance of ic package, pcb layout, the rate of surroundings airflow and temperature difference between junction to ambient. the maximum power dissipation can be calculated by following formula : p d(max) = (t j(max) ? t a ) / ja where t j(max) is the maximum operation junction temperature, t a is the ambient temperature and the ja is the junction to ambient thermal resistance. for recommended operating conditions specification of lc out 1 f = 2lc esr out 1 f = 2esrc z1 ss 1 f = 2rc p2 sp s sp 1 f = cc 2r cc ?? ?? + ?? () z2 1 f = 2r3r2c3 + () p1 1 f = 2 r3 r1 // r2 c3 + in out out full_load in sw in out out full_load in sw vv v 1 l i0.3vf vv v 1 i0.1vf ? < ? < ripple ripple(esr) ripple(c) ripple(esr) ripple ripple ripple(c) out sw v = v v v = iesr i v = 8c f + free datasheet http:///
12 ds8110a-00 may 2009 www.richtek.com RT8110A figure 7. derating curves for rt8110 package 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 0 25 50 75 100 125 ambient temperature (c) maximum power dissipation (w) single layer pcb sop-8 (exposed pad) layout guidelines pcb layout plays an important role for RT8110A since its switching frequency is 600khz. pcb with carefully layout can help to decrease switching noise for stable operation and better performance. the following guidelines can be used in pcb layout. ` feedback voltage divider resistors, compensation rcs, bootstrap capacitor, bootstrap diode and ceramic capacitors for vin and vcc should be placed close to the controller as possible. ` keep the power loops as short as possible. the current transition from one device to another at high speed causes voltage spikes due to the parasitic components on the circuit board. therefore, all the current switching loops should be kept as short as possible with wide traces to minimize the parasitic components. ` minimize the trace length between the mosfet and the controller. since the drivers are integrated in the controller, the driving path should be short and wide to reduce the parasitic inductance and resistance. ` place the ceramic capacitor physically close to the drain of the high-side fet and source of low-side fet. this can reduce the input voltage ringing at heavy load. ` place the output capacitor physically close to the load. this can minimize the impedance seen by the load, and then improves the transient response. ` the voltage feedback trace should be kept away from the switching node. keep the voltage feedback trace away from the phase node, inductor and mosfets due to, these switching node/ components are noisy. RT8110A, the maximum junction temperature is 125 c. the junction to ambient thermal resistance ja is layout dependent. for sop-8 (exposed pad) packages, the thermal resistance ja is 75 c/w on the standard jedec 51-7 four layers thermal test board. the maximum power dissipation at t a = 25 c can be calculated by following formula : p d(max) = (125 c - 25 c) / (75 c/w) = 1.333w for sop- 8 (exposed pad) the maximum power dissipation depends on operating ambient temperature for fixed t j(max) and thermal resistance ja . for RT8110A package, the figure 7 of derating curves allows the designer to see the effect of rising ambient temperature on the maximum power dissipation allowed. free datasheet http:///
13 ds8110a-00 may 2009 www.richtek.com RT8110A richtek technology corporation headquarter 5f, no. 20, taiyuen street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 fax: (8863)5526611 richtek technology corporation taipei office (marketing) 8f, no. 137, lane 235, paochiao road, hsintien city taipei county, taiwan, r.o.c. tel: (8862)89191466 fax: (8862)89191465 email: marketing@richtek.com information that is provided by richtek technology corporation is believed to be accurate and reliable. richtek reserves the ri ght to make any change in circuit design, specification or other related things if necessary without notice at any time. no third party intellectual property inf ringement of the applications should be guaranteed by users when integrating richtek products into any application. no legal responsibility for any said applications i s assumed by richtek. outline dimension a b j f h m c d i y x exposed thermal pad (bottom of package) 8-lead sop (exposed pad) plastic package dimensions in millimeters dimensions in inches symbol min max min max a 4.801 5.004 0.189 0.197 b 3.810 4.000 0.150 0.157 c 1.346 1.753 0.053 0.069 d 0.330 0.510 0.013 0.020 f 1.194 1.346 0.047 0.053 h 0.170 0.254 0.007 0.010 i 0.000 0.152 0.000 0.006 j 5.791 6.200 0.228 0.244 m 0.406 1.270 0.016 0.050 x 2.000 2.300 0.079 0.091 option 1 y 2.000 2.300 0.079 0.091 x 2.100 2.500 0.083 0.098 option 2 y 3.000 3.500 0.118 0.138 free datasheet http:///

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